The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to an improvement in a method for connecting a diffusion interconnection region to an interconnection layer in an MOS type device.
Heretofore, in an LSI (large-scale integrated circuit), an interconnection between elements has been carried out with a diffusion layer, a polysilicon layer and an aluminum layer. The connections between these interconnection layers, e.g., the connection between a diffusion layer and a polysilicon layer, has been performed by a so-called direct contact method which is also known as buried contact. However, the conventional connecting method employing the direct contact method has various problems. These will now be described with reference to the drawings.
FIG. 1A is a plan view showing part of an LSI having a direct contact portion. A gate electrode 101 and an interconnection layer 102, both of which are formed of poly-silicon, are disposed on a silicon substrate 100. Reference numerals 103 and 104 designate diffusion interconnection regions, which are, respectively, source and drain regions of an MOS transistor. A circuit equivalent to the device shown in FIG. 1A is indicated in FIG. 1B. The electrical connection between the layer 102 and the region 104 is performed in a direct contact portion 105 by a direct contact method.
FIGS. 2A to 2D are sectional views along A--A in FIG. 1A, showing schematic manufacturing steps of the device in FIG. 1A. For example, an oxide film 202 which becomes a gate oxide film is formed, for example, to a thickness of approx. 200 .ANG. by thermal oxidation on a p-type silicon substrate 201. Subsequently, with a predetermined resist pattern (not shown) as a mask, a direct contact region 203 of the thermal oxide film 202 is selectively etched and removed, for example, with NH.sub.4 F, and the surface of the silicon substrate of the portion is exposed (FIG. 2A).
Then, a poly-silicon layer 204 is formed on the overall surface by a CVD (chemical vapor deposition) method, and is heat treated in a POCl.sub.3 atmosphere, thereby diffusing phosphorus in the layer 204. At this time, the phosphorus is diffused in the substrate 201 in the direct contact region, and a diffusion region 205 which will become a direct contact portion is formed (FIG. 2B).
Subsequently, a photoresist pattern 206 is formed to cover those portions of the poly-silicon layer 204 which will become a gate electrode and an interconnection layer, and the layer 204 is removed by etching using the layer 206 as a mask. This etching may be performed with a reactive ion etching which employs an etchant, e.g., CCl.sub.4. The etching stops on the surface of the film 202 in the transistor portion, but does not reach the substrate 201. However, since there is not oxide film in the direct contact portion, a groove 207 is formed in the silicon substrate as shown in FIG. 2C.
Then, the portion of the film 202 which is not covered with the layer 204 is removed by etching to expose the substrate 201; thereafter an impurity, e.g., As is ion implanted in a dose of 3 to 4.times.10.sup.15 cm.sup.-2 at an accelerating voltage of 50 kV, and is heat treated, for example, at 1,000.degree. C. for approx. 30 min., thereby forming a source region 208a, a drain region 208b and a diffusion interconnection region 208c of an extension of the drain region 208b, all of which are n.sup.+ -regions (FIG. 2D). At this time, the impurity is injected to the inner surface of the groove 207, an n.sup.+ diffusion region 208d is formed in this portion, thereby electrically connecting a poly-silicon layer 209 to the region 208c.
According to the above-described method, however, the depth and the shape of the groove are not constant, but largely vary depending upon the conditions of etching and the time of an overetching. Therefore, the resistance value of the region 208d in this groove portion becomes remarkably irregular. When the groove 207 is largely formed, for example, in a circular sectional shape as shown in FIG. 2E, a diffusion region is not formed in the side walls of the groove 207, resulting in an electric isolation between the layer 209 and the layer 208c. Such a problem becomes an important problem as a junction depth becomes shallow upon microminiaturization of the device, causing a remarkable decrease in the yield of the LSI. Further, a crystal defect produced in the vicinity of the groove 207 by the reactive ion etching causes an increase in the junction leakage in the diffusion layer, resulting in a problem such as a decrease in the performance of the device.
The foregoing description relates to the case of an n-channel MOS transistor formed on the p-type silicon substrate. The following important problem exists in a so-called CMOS (Complementary MOS) circuit in which a p-channel MOS transistor and an n-channel MOS transistor are formed on the same substrate. In the portion of the p-channel transistor when an n.sup.+ -type is used as a poly-silicon layer, as shown, for example, in FIG. 3A, a source region 308a, a drain region 308b and a diffusion interconnection region 308c of an extension of the region 308b are p.sup.+ -type diffusion layers formed, for example, by boron ion implantation. However, a direct contact portion 305 is an n.sup.+ -type diffusion region (when steps similar to those in FIGS. 2A to 2D are employed), and a p-n junction is not formed between an n.sup.+ -type direct contact portion 305 and an n-type silicon substrate 301, and the portion 305 and the substrate 301 will shortcircuit.
When only a gate electrode 310 made of an n.sup.+ -type poly-silicon is initially formed, for example as shown in FIG. 3B, then a source region 308a, a drain region 308b and a diffusion interconnection region 308c made of a p.sup.+ -type diffusion layer and thereafter an n.sup.+ -type polysilicon layer 309 are formed, and then an n-type direct contact portion 311 are formed by a diffusion of an impurity from the layer 309, a p-n junction is formed between the portion 311 and the region 308c, and an ohmic contact is not formed.
Thus, when an interconnection layer made of n.sup.+ -type poly-silicon is used in the MOS circuit, the diffusion interconnection region and the poly-silicon layer could not be connected by the direct contact method in the p-channel MOS transistor. On the contrary, even when the interconnection layer made of a p.sup.+ -type poly-silicon is used, similar problems exist in the direct contact portion of the n-channel MOS transistor. These problems have caused a significant restriction in the design of the circuit.